The invention relates to delivering transactions between data buses in a computer system.
Computer systems often include one or more data buses that allow components of the computer system to communicate. For example, one common type of data bus is a Peripheral Component Interface (PCI) bus, which provides a special communication protocol between the computer system's CPU/main memory and peripheral components, such as small computer system interface (SCSI) devices and network interface cards (NICs). When system memory and the peripheral components (e.g., PCI devices) reside on different buses, a bridge is required to manage the flow of data transactions between the two buses. Typically, system memory and PCI devices each reside, at least indirectly, on PCI buses connected by a PCI-to-PCI bridge. PCI bus architecture is defined by the PCI Local Bus Specification, Revision 2.1 ("PCI Spec 2.1"), published in June 1995, by the PCI Special Interest Group, Portland, Ore., incorporated by reference. PCI-to-PCI bridge architecture is defined by the PCI-to-PCI Bridge Architecture Specification, Revision 1.0 ("PCI Bridge Spec 1.0"), published in April 1994, by the PCI Special Interest Group, also incorporated by reference.
Under the PCI Spec 2.1 and PCI Bridge Spec 1.0 standards, PCI bridges support two types of transactions: posted transactions (including all memory write cycles), which are completed on the initiating bus before they complete on the target bus, and delayed transactions (including memory read requests and I/O and configuration read/write requests), which are completed on the target bus before they are completed on the initiating bus. According to the PCI Spec 2.1, PCI-to-PCI bridges must strongly favor posted write transactions when determining the order in which transactions are to be performed on the target bus. The PCI Spec 2.1 requires that, in order to prevent lock-up conditions, the computer system must allow posted write cycles to bypass earlier-initiated delayed request cycles and must prevent delayed request cycles from bypassing earlier-initiated posted write cycles. This requirement holds even when a posted write transaction and a delayed request transaction occur between two different pairs of devices.
Referring to FIG. 1, a typical computer system includes a central processing unit (CPU) 10 and a main memory device 12 (including a memory controller) connected to a host bus 14. The host bus 14 communicates with a PCI bus 16 through a host-to-PCI bridge device 18. PCI bus 16 in turn communicates with another PCI bus 19 through a PCI-to-PCI bridge 20. PCI bus 16 is known as the "primary" PCI bus, and PCI bus 19 is known as the "secondary" PCI bus, because PCI bus 16 is closer hierarchically to the host bus 14 than is PCI bus 19.
Several peripheral devices, including video card 22, NIC 24, and PCI option card 26, are connected to the secondary PCI bus 19. Each device plugs in to a "slot" on the secondary PCI bus 19. The PCI option card 26 includes a PCI-to-PCI bridge device 28 and a PCI bus 30 of its own, which allows additional PCI devices to plug into a single slot on the secondary PCI bus 19. One or more PCI devices, such as SCSI device 32, may reside on the PCI option card 26. The PCI option card 26 operates as a "multi-threaded" device (i.e., a device that can maintain multiple delayed transactions simultaneously) when more than one PCI device is connected to its local PCI bus 30.
Transactions initiated by the CPU and targeting a device on the secondary PCI bus 19 are known as "downstream" transactions, and transactions initiated by a device on the secondary bus 19 and targeting main memory 12 are known as "upstream" transactions. Transactions initiated by a device on the secondary bus 19 and targeting another device on the secondary bus 19 are known as "peer-to-peer" transactions. Peer-to-peer transactions are not dealt with here.
According to PCI Spec 2.1, any posted write transaction initiated on the primary or secondary PCI bus and posted in the PCI-to-PCI bridge device 20 must be completed on the target bus before any subsequently-issued transaction can be completed on the target bus. In addition, any transaction that completes on the initiating bus before a delayed read transaction is initiated on the bus must be completed on the target bus before the delayed read transaction is completed on the target bus. Likewise, any transaction that is completed on the initiating bus after a delayed read transaction completes on the initiating bus must complete after the delayed read transaction on the target bus. Therefore, a memory write transaction posted in the PCI-to-PCI bridge 20 by SCSI device 22 must be completed on the primary PCI bus 16 before a later-issued delayed read request from NIC 24 is completed, and the posted memory write transaction must invalidate prefetch data associated with any earlier-issued delayed read transactions from NIC 24 (i.e., the prefetch data must be flushed from the PCI-to-PCI bridge 20 when the memory write transaction is posted).